The New Protagonist in the Compute War: When the "Super Node" Takes Center Stage

July 2026, Shanghai World Expo Exhibition Hall. A massive array formed by 16 compute cabinets occupied nearly the entire main wall of Huawei's booth – the actual Ascend 950 Super Node, with 1,024 compute cards densely embedded. Cables snaked through the racks like a neural network. Onlookers snapped photos and fired off questions in a never‑ending stream; some visitors pressed their palms against the glass, as if trying to sense the heat and the torrent of data radiating from the machine. This "most expensive wall," with a price tag easily reaching hundreds of millions of yuan, became the hardest‑core narrative at the 2026 World Artificial Intelligence Conference (WAIC), and for the first time gave the general public an intuitive glimpse that compute power is no longer about a single card – it is about an entire fleet.

A Super Node is not merely a brute‑force stacking of many chips. Physically, it consists of multiple compute nodes tightly interconnected through high‑performance protocols, behaving as "one computer" – meaning that all GPUs can collaborate on the same task without frequently exchanging intermediate results through external networks. Its core technical features include ultra‑high bandwidth (per‑card interconnect bandwidth exceeding 900 GB/s), ultra‑low latency (intra‑node communication latency below the microsecond level), and unified memory addressing. Taking Huawei's Ascend 950 Super Node as an example, it achieves an industry‑leading 256 TB of cross‑physical‑node unified memory address space. This means that a thousand cards can directly access remote data as if it were local video memory, completely overturning the cumbersome "manual data movement" approach of traditional distributed training.

This year's WAIC was essentially a collective debut of domestic Super Nodes. Beyond Huawei, Alibaba showcased its Zhenwu M890 × Pangu AL128 Super Node, compatible with both domestic and mainstream GPU chips, emphasising flexible scheduling for diverse compute resources. ZTE released its OEX Super Node supporting a multi‑GPU ecosystem, focusing on carrier‑grade reliability and cloud‑edge synergy. Biren Technology unveiled its next‑generation Super Node solution featuring NPO optical interconnects and a distributed decoupled architecture, supporting expansion up to 1,024 cards per Super Node – its optical interconnect technology is seen as a key direction for breaking through electrical‑signal transmission bottlenecks. Metax Tech debuted the "Xijing" S‑series Super Node, the first domestic solution to implement full‑link fault self‑recovery. Moore Threads publicly demonstrated its MTT C256 Super Node for the first time, supporting AI computing cluster expansion from ten thousand to one hundred thousand cards, and demonstrated a linear acceleration ratio of 92% when training a hundred‑billion‑parameter model at 128‑card scale. Sugon, meanwhile, displayed the all‑domestic 100,000‑card AI supercluster "Sugon 8000 (Dengfeng)," extending the Super Node concept from cabinet level to the scale of an entire data centre. A clear signal has been sent: the competitive dimension of domestic computing power has shifted from a single chip to the whole cabinet, cluster, and even the entire data centre.

Why did Super Nodes erupt so intensely in 2026? Behind this lies a fundamental shift in the training paradigm for large AI models. In the past few years, the main theme of the compute race was "single‑card breakout" – whoever had a faster chip and larger memory held the upper hand. But as model parameters leap from hundreds of billions to trillions, and training clusters expand from hundreds of cards to tens or even hundreds of thousands, the marginal return of single‑card performance is rapidly shrinking. The real bottleneck is no longer how fast a single card can compute, but whether tens of thousands of cards can "compute together." Taking the training of a trillion‑parameter MoE (Mixture of Experts) model as an example, the proportion of training time consumed by cross‑node communication has already surged from about 15% in earlier systems to over 50%. Even if single‑card compute power were doubled, without solving the communication bottleneck, overall training speed would improve by less than 10%. Hence, the Super Node, in essence, reconfigures the physical architecture to compress a "cluster" into a "giant computer," turning communication from a wall into a highway.

This trend is evident in industry data. Global AI server shipments in 2026 are expected to surpass 2 million units, a year‑on‑year increase of 55%, with the share of Super Node‑form‑factor whole‑cabinet shipments jumping from 12% last year to 31%. Leading cloud providers, large model developers, and government‑enterprise clients are all making scale‑compute procurement a standard requirement, and an increasing number of tender documents explicitly demand "support for Super Node‑level expansion." A senior executive at one compute‑service provider ran the numbers: a Super Node cabinet costs about 50% more than traditional servers, but due to communication efficiency gains, the effective compute power at thousand‑card scale can be improved by a factor of ten. "Customers see the math – training a GPT‑5‑class model with a Super Node can save two months and millions of dollars in electricity bills."

The Super Node wave has also stirred up huge ripples in the capital markets. From July 1 to 22, Unisplendour Corporation's share price rose 58%, pushing its market cap to 130 billion yuan; Inspur Information climbed 41%, nearing 140 billion yuan. Meanwhile, high‑speed interconnect chip supplier Shengke Communications gained over 35%, and optical module leader Zhongji Innolight logged a nearly 20% increase during the same period. Server manufacturer executives revealed that from the second half of 2026 through 2027, Super Nodes will see rapid volume growth. "When we talk with internet clients now, we're already discussing supply for 2027 and 2028. Their first question is always: 'If you can supply 100,000 cards, then we can talk.'" This practice of locking in long‑term capacity reflects strong downstream confidence in the Super Node architecture.

However, the Super Node boom has also exposed multiple tight spots in the supply chain. High‑end PCBs (printed circuit boards) have been in short supply throughout the year, with prices climbing sharply – some multi‑layer PCBs used in Super Node backplanes have seen price increases of three to four times or more. The value of PCBs per AI server is nearly ten times that of a general‑purpose server, and leading PCB makers already have their orders booked through 2027. At the same time, Super Nodes rely heavily on high‑speed copper cables and optical interconnects; the total length of high‑speed cabling inside a single cabinet can stretch several kilometres, directly pushing up utilisation rates for cable harness and connector suppliers. Core chips such as GPUs and HBM memory are also under tight supply, with TSMC's CoWoS advanced packaging capacity already fully booked for the second half of 2026. An even more practical challenge comes from power consumption and cooling: the peak power draw of a thousand‑card Super Node can easily exceed 1.5 megawatts, equivalent to the electricity consumption of a medium‑sized commercial complex. Liquid cooling has shifted from "optional" to "mandatory," and immersion cooling solutions are being rapidly validated by leading vendors.

Just as WAIC came to a close, AMD held its "Advancing AI 2026" conference in San Francisco on July 22–23. AMD launched the Zen 6 EPYC Venice processors and the MI455X series AI accelerators, the latter reaching 5.2 petaFLOPS at FP8 precision – nearly double the performance of the previous generation. More significantly, Microsoft announced it would deploy a large‑scale AI system based on AMD's "Helios" rack design, with an estimated investment of tens of thousands of GPUs, totalling between $5 billion and $10 billion – one of the most substantial AI training‑side orders AMD has ever secured. AMD CEO Lisa Su also revealed a collaboration with chip design firm Cerebras, combining AMD's Helios GPU server racks with Cerebras' wafer‑scale chips for an AI inference solution, aiming to challenge NVIDIA's dominance with a "wafer‑scale + Super Node" combination.

At the same time, Google is developing a new server chip codenamed "Frozen" that hard‑codes the Gemini model directly into the silicon. The idea is to make the hardware "understand" the specific model's operator graph and memory access patterns from the design stage, thereby reducing scheduling overhead and redundant data transfers at runtime. This represents a completely different AI chip direction – moving from "supporting all models" to "deep optimisation around mainstream models." If successful, the meaning of Super Nodes will be redefined: no longer a generic physical stacking of interconnects, but a "customised compute matrix" tailored to specific model architectures.

From the collective Super Node showcase by Chinese vendors at WAIC, to AMD's and Microsoft's massive AI compute deployments, to Google's exploration of "model‑defined chips" – the computing industry is undergoing a profound transformation from "single‑card competition" to "system‑level competition." The industry no longer solely chases peak chip FLOPS; cost per token, total cost‑effectiveness, and cluster linear acceleration ratios are emerging as the new key metrics. The Super Node is not the final destination; it is merely the beginning of a larger saga: the future of compute competition may well be determined by overall data‑centre energy efficiency and the depth of software ecosystems. And that "most expensive wall" – perhaps it serves as the most vivid illustration of this transition. It tells us that when compute power ceases to be about a single card, an entire era is being rewritten from the ground up.